Title :
Some optimal schemes for ALU implementation in VLSI technology
Author :
Oklobdzija, Vojin G. ; Barnes, Earl R.
Author_Institution :
IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598
Abstract :
An efficient scheme for carry propagation in an ALU implemented in n-MOS technology is presented. An algorithm that determines the optimum division of the carry chain of a parallel adder for various data path sizes is developed. This yields an implementation of a fast ALU which due to its regular structure occupies a modest amount of silicon. The speed of the implementation described is comparable to the carry look-ahead scheme. Our method is based on the optimization of the carry path implemented in n-MOS technology but the results can be applied to other technologies.
Keywords :
Adders; Delay; Histograms; Logic gates; Optimization; Propagation delay; Very large scale integration;
Conference_Titel :
Computer Arithmetic (ARITH), 1985 IEEE 7th Symposium on
Conference_Location :
Urbana, IL,
DOI :
10.1109/ARITH.1985.6158969
