DocumentCode
3401945
Title
Design considerations for ADC-based backplane receivers
Author
Hayun Chung ; Gu-Yeon Wei
Author_Institution
Dept. of Electron. & Electr. Eng., Keio Univ., Yokohama, Japan
fYear
2011
fDate
7-10 Aug. 2011
Firstpage
1
Lastpage
4
Abstract
High-speed ADC-based backplane receivers often suffer from high power consumption and complexity and require careful designs. This paper discusses circuit- and system-level design considerations for such receivers. A low-power, high-speed front-end ADC circuit and a high-level design-space exploration of ADC-based receivers are presented.
Keywords
analogue-digital conversion; low-power electronics; network synthesis; receivers; ADC-based backplane receivers; circuit-level design; high-speed front-end ADC circuit; low-power front-end ADC circuit; system-level design; Data models; Educational institutions; Receivers; Transceivers;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on
Conference_Location
Seoul
ISSN
1548-3746
Print_ISBN
978-1-61284-856-3
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2011.6026280
Filename
6026280
Link To Document