A 20Gb/s triple-mode (PAM-2, PAM-4, and duobinary) transmitter

Increasing data rates over electrical channels with significant frequency dependent loss is difficult due to excessive inter-symbol interference (ISI). In order to achieve sufficient link margins at high rates, I/O system designers implement equalization in the transmitters and are motivated to consider more spectrally-efficient modulation formats relative to the common PAM2 scheme, such as PAM4 and duobinary. This paper reviews when to consider PAM4 and duobinary formats, as the modulation scheme which yields the highest system margins at a given data rate is a function of the channel loss profile. A 20Gb/s triple-mode transmitter capable of efficiently implementing these three common modulation schemes and three-tap feed-forward equalization is presented. A power efficient quarter-rate duobinary precoder circuit is proposed which provides significant timing margin improvement relative to full-rate precoders. Simulation results in a 90nm CMOS technology compare the different modulation schemes over three backplane channels with different loss profiles.