Hybrid CMOS/SEED smart pixel array for 2-D parallel pipeline operations

We are developing a free-space digital optics (FSDO) system using hybrid CMOS/SEED technology to demonstrate 2-D parallel pipelining of digital computing and interconnection operations. This system optically moves 2-D arrays (frames) of digital data between chips containing mesh-connected smart pixel arrays (SPAs). The smart pixels perform electronic digital operations on the incoming data frames and/or data frames stored within the pixels. The chip design is flexible in that it can provide conversions between 1-D electrical and 2-D optical data formats, data frames manipulation and computations, optical 2-D parallel transfer of data frames and serial-parallel conversion. We have designed an optomechanical system that will house CMOS/SEED chips to construct a 2-D pipeline processor. The smart pixel design is based on the digital optical cellular image processor (DOCIP) architecture which excels at performing image processing algorithms and other data-level parallel problems. We have targeted several applications in image processing and simulated the implementation of algorithm on our smart pixel chip.