Time and space-multiplexed compilation challenges for dynamically reconfigurable processors

This paper presents our dynamically reconfigurable processor (DRP) and its compiler. We first introduce our DRP architecture, which is suitable for both parallelizable and control-intensive code segments since it has a stand-alone finite state machine that switches “contexts” consisting of many processing elements (PEs). Then, some optimization techniques used in the compiler are explained, such as a loop pipelining, iterative synthesis technique to shorten wire delay, and a technique to achieve higher area efficiency by utilizing the benefit of having multiple contexts. Lastly, two products are shown as application examples.