Design techniques for ultra low-power phase-locked loops

Ultra-low power frequency synthesizers resilient to environmental variations are desired in various wireless microsensor applications where power consumption and reliability are important performance metrics. This paper reviews the design techniques for a ultra-low power PLLs employing low-supply voltage and charge recycling techniques. Design challenges such as minimizing sensitivity to environmental variations are addressed for low-voltage and charge-recycling operation, which include adaptive body-biasing and implicit negative feedback DC-DC conversion.