Technology-friendly phase-locked loops

This paper presents recent architectures of the phase-locked loop (PLL) systems which relax technology dependency and provide robust, low-cost frequency generation. The first part of the paper discusses architecture advantages of the dual-path PLL which significantly reduces loop bandwidth variation. The second part of the paper reviews recent hybrid PLL architectures which do not employ the time-to-digital converter (TDC) but still offer technology scalability and leakage current immunity.