An Architecture for a 7 × 7-bit multiple-radix multiplier building block

Novel multiple radix architectures for 7N × 7N integer multiplications, where N = 2^k and k is a non-negative integer, based on recent developments involving multiple radix representation of numbers is presented. Hardware implementations for a 7 × 7 bit multiple-radix multiplier is provided, followed by larger multiplier architectures that employ the 7×7 architecture as a building-block based on the Karatsuba Algorithm. The methodology employed for prototyping the multiplier circuits using Xilinx FPGA devices is described. Measured results in terms of speed and area complexity from on-chip physical FPGA realizations are provided. This recursive architecture provides a new method for building multiple-radix parallel hardware multipliers operating on large integer multiplicands with potential future applications in areas such as computational number theory, digital arithmetic and computer security.