Minimum detectable capacitance in capacitive readout circuits

In this paper, accurate equations are presented to calculate the capacitance resolution in the readout circuits exploiting different techniques to reduce the circuit low-frequency noise. The circuit parameters and trade-offs affecting the capacitance resolution are comprehensively involved in these equations. Transistor level simulations are performed with a 0.18 μm CMOS technology using Spectre RF to verify the obtained equations. The results of comparing two utilized common techniques, so called correlated double sampling (CDS) and chopper stabilization (CHS), reveal that employing the combination of these techniques results in the minimum resolution variation as the input parasitic capacitance is changed.