• DocumentCode
    3402943
  • Title

    Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology

  • Author

    Po-Yen Chiu ; Ming-Dou Ker

  • Author_Institution
    Nanoelectron. & Gigascale Syst. Lab., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
  • fYear
    2013
  • fDate
    4-6 Sept. 2013
  • Firstpage
    33
  • Lastpage
    36
  • Abstract
    The novel 2×VDD NOT, NAND, and NOR logic gates have been designed and implemented in a nanoscale CMOS process with only 1×VDD devices. With the proposed dynamic source bias technique, the logic gates can be designed to have 2×VDD tolerant capability. Thus, the new 2×VDD logic gates can be operated under 2×VDD voltage environment without suffering the gate-oxide reliability issue.
  • Keywords
    CMOS logic circuits; logic design; logic gates; nanoelectronics; NAND logic gates; NOR logic gates; NOT logic gates; dynamic source bias technique; gate-oxide reliability; logic gate design; nanoscale CMOS technology; Abstracts; CMOS integrated circuits; Logic gates; MOSFET; Nanoscale devices; Reliability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOC Conference (SOCC), 2013 IEEE 26th International
  • Conference_Location
    Erlangen
  • ISSN
    2164-1676
  • Type

    conf

  • DOI
    10.1109/SOCC.2013.6749656
  • Filename
    6749656
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3402943