DocumentCode
3403016
Title
A fast multi-operand multiplication scheme
Author
Kobayashi, Hideaki
Author_Institution
Electrical and Computer Engineering Department University of South Carolina Columbia, SC 29208
fYear
1981
fDate
16-19 May 1981
Firstpage
246
Lastpage
250
Abstract
Recent developments in integrated circuit technology have made efficient schemes for computer arithmetic possible. This paper discusses a generation-summation scheme for fast multi-operand multiplication. Synthesis of three-operand multipliers utilizing a single type of standard LSI device is also discussed.
Keywords
Adders; Arrays; Delay; Large scale integration; Logic gates; Radiation detectors; Read only memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Arithmetic (ARITH), 1981 IEEE 5th Symposium on
Conference_Location
Ann Arbor, MI, USA
Type
conf
DOI
10.1109/ARITH.1981.6159279
Filename
6159279
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