Title :
A fast multi-operand multiplication scheme
Author :
Kobayashi, Hideaki
Author_Institution :
Electrical and Computer Engineering Department University of South Carolina Columbia, SC 29208
Abstract :
Recent developments in integrated circuit technology have made efficient schemes for computer arithmetic possible. This paper discusses a generation-summation scheme for fast multi-operand multiplication. Synthesis of three-operand multipliers utilizing a single type of standard LSI device is also discussed.
Keywords :
Adders; Arrays; Delay; Large scale integration; Logic gates; Radiation detectors; Read only memory;
Conference_Titel :
Computer Arithmetic (ARITH), 1981 IEEE 5th Symposium on
Conference_Location :
Ann Arbor, MI, USA
DOI :
10.1109/ARITH.1981.6159279
