Design of a CMOS track-and-hold amplifier for a 6-bit 1-GS/s interpolating flash ADC

Author

Geoghegan, K.B. ; Heedley, P.L. ; Matthews, T.W. ; Michael, S.

Author_Institution

Dept. of Electr. & Comput. Eng., Naval Postgrad. Sch., Monterey, CA, USA

fYear

2011

fDate

7-10 Aug. 2011

Firstpage

1

Lastpage

4

Abstract

The design of a CMOS track-and-hold amplifier (THA) for a 6-bit 1-GS/s interpolating flash ADC is presented. Since the goal of the overall project was to determine the performance of a new ADC calibration architecture, the THA was prohibited from being the limiting factor in the performance of the ADC; consequently the THA was required to have at least 56dB of signal-to-noise and distortion ratio (SNDR) at the Nyquist frequency. The THA architecture, design methodology, and supporting simulation results will be presented.

Keywords

CMOS digital integrated circuits; amplifiers; analogue-digital conversion; integrated circuit design; sample and hold circuits; ADC calibration architecture; CMOS track-and-hold amplifier design; Nyquist frequency; SNDR; THA architecture; bit rate 1 Gbit/s; design methodology; interpolating flash ADC; signal-to-noise-and-distortion ratio; Bandwidth; CMOS integrated circuits; Silicon; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on

Conference_Location

Seoul

ISSN

1548-3746

Print_ISBN

978-1-61284-856-3

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2011.6026340

Filename

6026340