A low-glitch and small-logic-area Fibonacci Series DAC

A novel Digital-to-Analog Converter (DAC) utilizing Fibonacci Series is presented in this paper. The ratios of successive weights are smaller than those of binary DAC and larger than those of unary DAC. The features of the proposed DAC are lower glitch-energy than a binary DAC and the number of logic gates is less than a unary DAC. In the proposed DAC in 0.18μm CMOS process, the glitch-energy of the proposed DAC can be reduced by 75% compared to that of binary DAC, and the number of logic gates can be achieved an around 42% reduction compared to that of the unary DAC. We fabricated a prototype 6-bit Fibonacci Series DAC in order to confirm the operation.