An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder

Reversible logic has captured significant attention in recent time as reducing power consumption is the main concern of digital logic design. It consumes less power by recovering bit loss from its unique input-output mapping. This paper presents the design of an optimal reversible fault tolerant carry look-ahead adder. We present an algorithm to design a generalized n-bit carry look-ahead adder, where n is the number of bits of the operands. A new technique to calculate the quantum gate complexity of quantum circuits has also been proposed in the paper. In addition, several theorems on the numbers of garbage outputs, quantum cost, quantum gate complexity and delay of the fault tolerant reversible carry look-ahead adder have been presented to show its optimality. Simulation using Microwind DSCH software has been shown to verify the correctness of the function of the proposed carry look-ahead adder. The comparative study shows that the proposed design is much better than the existing approach considering all the efficiency parameters of reversible circuit design which includes numbers of gates, quantum cost, delay, quantum gate complexity and garbage outputs. The proposed 8-bit reversible fault tolerant carry look-ahead adder improves 94.9% on the number of gates, 92.4% on the quantum cost, 93.2% on the garbage outputs and 14.5% on the delay than the existing design.