• DocumentCode
    3403166
  • Title

    Algorithms for parallel addition and parallel polynomial evaluation

  • Author

    Papachristou, Christos A.

  • Author_Institution
    Department of Electrical and Computer Engineering University of Cincinnati Cincinnati, Ohio 45221
  • fYear
    1981
  • fDate
    16-19 May 1981
  • Firstpage
    256
  • Lastpage
    263
  • Abstract
    This paper presents two related algorithms for implementing parallel n-bit binary addition and evaluating n-th degree polynomials, respectively. The approach taken makes use of an iterative construction, the computation tree. The algorithms are particularly effective for moderate values of n and are in accord with well-known asymptotic bounds. In the case of n-bit addition, the implementations constitute look-ahead tree circuits of r-input standard logic elements. Extensions to modular tree structures for lookahead adders are also considered. In the case of parallel polynomial evaluation, the operations of ordinary addition and multiplication are assumed with the capability to employ r arguments simultaneously.
  • Keywords
    Adders; Computers; Educational institutions; Logic gates; Neodymium; Polynomials; Tiles;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Arithmetic (ARITH), 1981 IEEE 5th Symposium on
  • Conference_Location
    Ann Arbor, MI, USA
  • Type

    conf

  • DOI
    10.1109/ARITH.1981.6159286
  • Filename
    6159286