A novel 8 bit open loop residue amplifier based pipeline ADC using a single fully differential current conveyor and foreground calibration

Author

Balasubramaniam, Harish ; Hofmann, Klaus

Author_Institution

Integrated Electron. Syst. Lab., Tech. Univ. Darmstadt, Darmstadt, Germany

fYear

2011

fDate

7-10 Aug. 2011

Firstpage

1

Lastpage

4

Abstract

The paper presents a 8 bit, 1.5b/stage fully differential pipeline ADC using a single second generation current conveyor (CCII) per stage. The fully differential configuration uses a passive common mode suppression technique to eliminate the need for common mode feedback circuits. Furthermore, simple foreground calibration is used to correct errors due to process induced mismatch and changes in gain, offset voltages. Simulation results show that the ADC works for differential inputs of (-500m, 500m) at 10MHz with 7.1 ENOB. The INL and DNL are within ± 0.8LSB and ± 0.5LSB respectively. The total power of the analog part is 5.5mW in a 1V/90nm TSMC process.

Keywords

analogue-digital conversion; calibration; current conveyors; 8-bit open loop residue amplifier; CCII; TSMC process; common mode feedback circuits; foreground calibration; full- differential current conveyor; offset voltages; passive common mode suppression technique; pipeline ADC; power 5.5 mW; second generation current conveyor; size 90 nm; voltage 1 V; CCII; Current Conveyors; Foreground Calibration; Fully Differential; Pipeline ADC;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on

Conference_Location

Seoul

ISSN

1548-3746

Print_ISBN

978-1-61284-856-3

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2011.6026362

Filename

6026362