Plenary speaker: “Power-centric timing optimization for low power CPU hardening”

Achieving the best performance, power and area (PPA) for processor cores is both a science and an art. A variety of interacting factors affect the achievable performance, power and area of a processor implemented in an SoC. In this session learn how to optimize the Quad-Core ARM^® Cortex™-A7 MPCore™ processor for the best power efficiency targeted for entry mobile and other power-sensitive products.Shared best practices leverage Synopsys´ high-performance core (HPC) methodology, including optimizations for power as a primary requirement to be managed at each step in the flow; from synthesis, placement, clock and routing, to post-route timing closure. Low power capabilities introduced here are augmented with aggressive power management of library VT classes and timing targets. The power-centric high-performance core methodology will be illustrated through a reference implementation of a quad core Cortex-A7 processor with ARM POP(TM) technology for core-hardening acceleration on TSMC 28HPM process. The final product is a strong starting point for designing the `LITTLE´ core in a big.LITTLE™ technology-based SoC, or as a stand-alone application processor for cost-sensitive markets.