DLL-based programmable clock multiplier using differential toggle-pulsed latch

In this paper, a programmable clock multiplier based on delay-locked loop is presented. It provides a flexible set of multiplying factors for differential clock generation. With the aid of the newly proposed gated short pulse generator and the differential toggle-pulsed latch, the measured output frequency of the clock multiplier implemented in CMOS 0.18-μm technology is within 0.15~1.8 GHz. The core circuit occupies an area of 0.076 mm². The rms and peak-to-peak jitter of the multiplied output clocks at 1.6 GHz is 1.45 and 12.36 ps, respectively.