Sample rate conversion using Walsh-transform for radar receiver

Current SRC methods can consume a large fraction of the digital signal processor resources leaving limited computational power for other tasks. Reducing the computational requirements for SRC is a key element for the success and profitability of SWR systems. An efficient decimation architecture using Walsh transform for HF surface wave radar receivers is presented. The proposed takes into consideration the complexities of algorithm due to the relatively high data rate and the intensive filter operations involved in commonly used decimators, which substitute multiplication-addition for addition-subtraction imposed on filter. Performances illustrative are compared with that of other similar decimators. Experiments results show that the new decimators outperform others, which is suited for real time signal processing in DSP, such as ADSP2 1060.