Title :
Sleep transistor design in 28nm CMOS technology
Author_Institution :
Cadence Design Syst., Dallas, TX, USA
Abstract :
Significant changes in transistor´s power-performance characteristic and cross-corner variations in 28nm CMOS technology prompt the need for a new look at sleep transistor design guidelines. This paper evaluated impacts of back-bias, Vt, and gate length and width on sleep transistor design quality. Recommendations were proposed for production design considerations.
Keywords :
CMOS integrated circuits; MOSFET; CMOS technology; back-bias; cross-corner variations; gate length; production design; size 28 nm; sleep transistor design quality; transistor power-performance characteristic; Abstracts; CMOS integrated circuits; CMOS technology; Fingers; Logic gates; MOS devices; Switches;
Conference_Titel :
SOC Conference (SOCC), 2013 IEEE 26th International
Conference_Location :
Erlangen
DOI :
10.1109/SOCC.2013.6749701
