Title :
Data buffer performance for sequential Prolog architectures
Author_Institution :
Comput. Syst. Lab., Stanford Univ., CA, USA
fDate :
30 May-2 Jun 1988
Abstract :
Several local data buffers are proposed and measurements are presented for variations of the Warren abstract machine (WAM) architecture for Prolog. Choice-point buffers, stack buffers, split-stack buffers, multiple-register sets, copyback caches, and smart caches are examined. Statistics collected from four benchmark programs indicate that small conventional local memories perform quite well because of the WAM´s high locality. The data memory performance results are equally valid for native code and reduced instruction set implementations of Prolog
Keywords :
PROLOG; buffer storage; computer architecture; performance evaluation; Warren abstract machine; benchmark programs; choice point buffers; copyback caches; data buffer performance; data memory performance results; local data buffers; multiple-register sets; reduced instruction set; sequential Prolog architectures; smart caches; split-stack buffers; stack buffers; Artificial intelligence; Bandwidth; Computer architecture; Computer buffers; Databases; Laboratories; Logic programming; Program processors; Registers; Statistics;
Conference_Titel :
Computer Architecture, 1988. Conference Proceedings. 15th Annual International Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
0-8186-0861-7
DOI :
10.1109/ISCA.1988.5254
