Low-power signal integrity trainings for multi-clock source-synchronous memory systems

Advanced high-speed multi-clock source-synchronous systems such as GDDR5 employ different trainings to ensure the signal integrity for high bandwidth applications. Through these trainings proper timing relationships among data and clocks are defined in the initialization phase. In this paper, a multi-clock synchronization training using phase interpolator (PI)-based phase-locked loop (PLL) architecture is proposed, which consumes 11.7 times less power and 27 times less area than other works. In addition, an adaptive equalization training is introduced for a GDDR5 memory system to compensate for inter-symbol interference (ISI). For the low power design, the equalizers are applied only in the memory controller utilizing the existing GDDR5 memory interface. This system architecture aimed of low-power design is verified by using least mean square (LMS) and pilot signal/peak detection. Results show that LMS algorithm improves the vertical and horizontal eye opening by more than 30% and 10%, respectively.