• DocumentCode
    3403881
  • Title

    Equal length routing

  • Author

    Blair, Gerard M.

  • Author_Institution
    Design Implementation, LSI Corp., Allentown, PA, USA
  • fYear
    2013
  • fDate
    4-6 Sept. 2013
  • Firstpage
    331
  • Lastpage
    335
  • Abstract
    Equal length routing for multi-bit buses is valuable in supporting asynchronous communication protocols; it is challenging in a floorplan with multiple hardmacros and narrow channels. We present a three stage flow which takes a text description of each bus´ channels and creates an equal number of equally spaced inverters to implement equal length routing for multi-bit buses: resulting in process-invariant, equal flight times.
  • Keywords
    field buses; network routing; protocols; system buses; asynchronous communication protocols; bus channel text description; equal-flight times; equal-length routing; equally-spaced inverters; multibit bus; process-invariant times; three-stage flow; Clocks; Diamonds; Topology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOC Conference (SOCC), 2013 IEEE 26th International
  • Conference_Location
    Erlangen
  • ISSN
    2164-1676
  • Type

    conf

  • DOI
    10.1109/SOCC.2013.6749711
  • Filename
    6749711
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3403881