DocumentCode
3403911
Title
Noise immunity improvement in the RESET signal of DDR3 SDRAM memory module
Author
Seung Mo Jung ; Jong Hyun Seok ; Ho Jin Yoo ; Do Hyung Kim ; You Keun Han ; Woo Seop Kim ; Joo Sun Choi ; Jun Dong Cho
Author_Institution
Sungkyunkwan Univ., Suwon, South Korea
fYear
2013
fDate
4-6 Sept. 2013
Firstpage
343
Lastpage
348
Abstract
In asynchronous RESET signal in DDR3 SDRAM memory module, noise is sensitive at certain specific frequency with low voltage. In this paper, our comprehensive measurement verifies that the RESET signal with specific frequency is changed into “Low” due to the noise (i.e., resonance and crosstalk) that results in system halt. Furthermore, we provide a design guideline to JEDEC memory module PCB sponsors to remedy the noise problem in the RESET signal with providing a specific design topology.
Keywords
DRAM chips; asynchronous circuits; integrated circuit design; integrated circuit measurement; integrated circuit noise; modules; printed circuit design; DDR3 SDRAM memory module; JEDEC memory module PCB; asynchronous RESET signal; crosstalk; noise immunity improvement; Abstracts; SDRAM; Switches; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference (SOCC), 2013 IEEE 26th International
Conference_Location
Erlangen
ISSN
2164-1676
Type
conf
DOI
10.1109/SOCC.2013.6749713
Filename
6749713
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