Low power fast cryogenic CMOS circuit for digital readout of single electron transistor

We present a cryogenic CMOS circuit with significant performance improvements compared to previously proposed single-shot Single Electron Transistor readout circuit. The new readout architecture developed on commercial 0.5μm SOI CMOS process is designed to operate at 4.2K temperature and detect the SET signal current as low as 200pA. In addition to very low signal levels, the design process is complicated due to severe power consumption limitations at low temperature and μV level drain-source compliance requirement of the SET. The design addresses the low-temperature CMOS irregularities found in published literature and even under the design restrictions and SET specifications, our circuit shows successful digital detection of a SET event with only ~ 520ns delay and consumes as low as 76μW power. In addition to speed improvement over previous design (detection time more than 10μs), this design is more robust and tolerant to biasing variations.