Design and implementation of MIMO WLAN deinterleaver with bit-reversed input

This paper discusses a novel design for MIMO IEEE802.11n WLAN deinterleaver which is able to omit the need of reordering after FFT process. It combines reordering process and deinterleaving process in the deinterleaver. Thus RAM and latency cost for reordering can be eliminated. In this way, overall system implementation area and latency cost can be minimized. Proposed deinterleaver employs combination of LUT-AGU technique. The proposed deinterleaver is able to minimize the LUT cost in the price of higher design complexity and higher logic area cost. The design is implemented on 90nm CMOS ASIC technology. The logic area cost is 0.0929mm² and correspond gates count is 16.79 KGE. This area result is four times lower than other LUT technique. The power consumption is 2.43mW at 160MHz. This is the lowest compare to the other works.