Ultra high-throughput architectures for hard-output MIMO detectors in the complex domain

In this paper, a novel hard-output detection algorithm for the complex multiple-input multiple-output (MIMO) detectors is proposed, which results in a significant throughput enhancement, a near-ML performance, and an SNR-independent fixed-throughput. Moreover, a high-throughput VLSI implementation is proposed, which is based on a novel method of the node generation and sorting scheme. The proposed design achieves the throughput of 10Gbps in a 0.13 μm CMOS process, which is the highest throughput reported in the literature for both the real and the complex domains. Synthesis results in 90nm CMOS also show that the proposed scheme can achieve the throughput of up to 15Gbps. Moreover, the FPGA implementation of the proposed algorithm on Virtex-4 XC4VFX140 proves the sustained throughput of 2Gbps at 83MHz clock frequency. The proposed architecture can easily be extended to high-order constellation schemes and can be tailored for low-power/lower-area applications at the expense of a lower detection throughput.