A fully integrated CMOS high-speed amplifier

Author

Fuhua, Li ; Changqing, Wang ; Zhengfan, Li

Author_Institution

Sch. of Electron. & Inf., Suzhou Univ., China

Volume

2

fYear

2005

fDate

4-7 Dec. 2005

Abstract

To achieve wide-bandwidth performance, an on-chip high-speed limiting amplifier is proposed employing a low-pass network topology. To avoid the parasitic effects of the on-chip spiral inductor, several short circuit coplanar strip line stubs fabricated with thicker top metal layer are used as passive inductors. The gain and bandwidth of the amplifier is studied employing a simplified MOSFET model. Finally, a test amplifier with a bandwidth of 6 GHz, gain of 15 dB and power dissipation of 70 mW is fabricated with the standard 1.8-V 0.18-μm digital CMOS process.

Keywords

CMOS digital integrated circuits; MOSFET; inductors; microwave amplifiers; network topology; semiconductor device models; strip lines; 0.18 micron; 1.8 V; 15 dB; 6 GHz; 70 mW; CMOS high-speed amplifier; MOSFET model; coplanar strip line stubs; coplanar stripline; digital CMOS process; high-speed limiting amplifier; low-pass network topology; on-chip spiral inductor; passive inductors; power dissipation; Bandwidth; Broadband amplifiers; Circuit testing; Inductors; MOSFET circuits; Network topology; Network-on-a-chip; Power amplifiers; Semiconductor device modeling; Spirals; Coplanar stripline; High-speed limiting amplifier; Low-pass network;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference Proceedings, 2005. APMC 2005. Asia-Pacific Conference Proceedings

Print_ISBN

0-7803-9433-X

Type

conf

DOI

10.1109/APMC.2005.1606410

Filename

1606410