Reliability and performance-aware 3D SRAM design

Author

Pathak, Mohit ; Sung Kyu Lim

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2011

fDate

7-10 Aug. 2011

Firstpage

1

Lastpage

4

Abstract

In 3D integrated circuits, through-silicon-vias (TSVs) are used to connect different dies stacked on top of each other. These TSVs occupy significant silicon area and are many times larger than gates. Depending on the fabrication technique, TSVs can have different area and fabrication cost. TSVs can also cause reliability challenges for 3D ICs by reducing the yield of the chip. In this paper, we discuss how to perform physical design of bank-level 3D SRAM. We show that a tradeoff exists in terms of reliability and performance for 3D SRAMs. We also show the impact of via-first vs via-last TSVs on the layout quality of 3D SRAM designs. All our results are based on GDSII based layouts. Based on our results different SRAM organizations maybe chosen based on reliability versus performance tradeoff.

Keywords

SRAM chips; integrated circuit design; integrated circuit reliability; integrated circuit yield; three-dimensional integrated circuits; 3D integrated circuits; GDSII based layouts; bank-level 3D SRAM; fabrication cost; integrated circuit reliability; integrated circuit yield; performance-aware 3D SRAM design; through-silicon-vias; Random access memory; Reliability engineering; Three dimensional displays; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on

Conference_Location

Seoul

ISSN

1548-3746

Print_ISBN

978-1-61284-856-3

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2011.6026429

Filename

6026429