A comparative study of biasing circuits for an inductorless wideband Low Noise Amplifier

Author

Dores, Jose M. ; Alvarez, E.B. ; Martins, Manuel A. ; de la Rosa, Jos M. ; Fernandes, Jorge R.

Author_Institution

Analog & Mixed Circuit Group, Tech. Univ. Lisbon, Lisbon, Portugal

fYear

2011

fDate

7-10 Aug. 2011

Firstpage

1

Lastpage

4

Abstract

In this paper we present a comparative study of different biasing versions of an inductorless low-area Low Noise Amplifier (LNA). With this study, we intend to determine the most suitable biasing circuit to achieve the best LNA performance. The LNAs under study are simulated in two different CMOS processes, 130 nm and 90 nm. The supply voltage is 1.2 V. The best LNA implemented in 130 nm achieves a bandwidth of 2.94 GHz with a flat voltage gain (A_v) of 16.5 dB and a power consumption of 3.2 mW. The same LNA topology implemented in 90 nm technology has a bandwidth of 11.2 GHz, voltage gain of 16.6 dB and consumes 1.9 mW. Both LNAs have input impedance matching and have a noise figure below 2.4 dB at 2.4 GHz.

Keywords

CMOS analogue integrated circuits; impedance matching; low noise amplifiers; CMOS process; LNA performance; LNA topology; bandwidth 11.2 GHz; bandwidth 2.94 GHz; biasing circuit; gain 16.5 dB; gain 16.6 dB; impedance matching; inductorless low-area low noise amplifier; inductorless wideband low noise amplifier; power 1.9 mW; power 3.2 mW; size 130 nm; size 90 nm; voltage 1.2 V; Inductors;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on

Conference_Location

Seoul

ISSN

1548-3746

Print_ISBN

978-1-61284-856-3

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2011.6026435

Filename

6026435