Run-time FPGA health monitoring using power emulation techniques

In recent years research on long-term reliability of FPGAs intensified significantly. This results from the broad usage of these devices for applications that come with high long-term stability constraints while being physically inaccessible. Several error checking and detection methods have been published to cope with degradation over time but these either force the FPGA to halt for exhaustive tests or their coverage decreases significantly. This paper presents an early view on a multi-disciplinary approach for run-time reliability monitoring and self-repairing using state-of-the-art power-emulation and FPGA partial reconfiguration techniques. Furthermore we propose a novel device aging detection mechanism using these power emulation techniques. It is meant to provide an outlook on the current state-of-the-art and future possibilities using these techniques for a combined reliability effort.