HDL to SP conversion containing interconnect effects using SAD matrix

This paper introduces a new method to take into account the effects of interconnects in simulations of modern digital circuits. It is possible in this technique to take into account the impact of interconnects in early stages of high level design with no need of layout information. In this method the description of the circuit is modeled as a graph. This graph is shown in a new shape of adjacency matrix which is optimized in terms of number of vertices rather than a regular adjacency matrix. We call this new matrix the sad-mat. The sad-mat is stored in computer memory by means of linked lists. The algorithm used by the previous work on HDL to SP Conversion was NP-Complete. The proposed method in this paper uses a new algorithm which has complexity O(log n) where n is total number of primitive inputs and outputs and none- primitive nodes in the circuit. This new method has been applied to many standard ISCAS circuits and the output results have shown a significant improvement in terms of running time. The proposed method is implemented as a CAD tool called H²SP. ISCAS circuits are also used to verify the H²SP´s algorithm.