Multi-merged-switched redundant capacitive DACs for 2b/cycle SAR ADC

Author

Jianyu Zhong ; Yan Zhu ; Sai-Weng Sin ; Seng-Pan U ; Martins, Rui P.

Author_Institution

State-Key Lab. of Analog & Mixed Signal VLSI, Univ. of Macau, Macao, China

fYear

2011

fDate

7-10 Aug. 2011

Firstpage

1

Lastpage

4

Abstract

This paper introduces a novel switch approach for redundant capacitive DACs of a 2b-per-cycle SAR ADC. By using the proposed multi-merged switching algorithm, the conventional trial-and-error search procedure is prevented, which leads to significant switching energy and DAC settling time reductions. The conversion power and speed analysis are presented, which is also verified in behavior simulations of a 6-bit 2b/cycle SAR ADC. The simulation results show that the proposed method can achieve about 37% power saving as compared to the conventional one.

Keywords

analogue-digital conversion; digital-analogue conversion; 2b/cycle SAR ADC; DAC settling time reduction; behavior simulation; conversion power; multimerged-switched redundant capacitive DAC; power saving; speed analysis; successive approximation register; switching energy reduction; trial-and-error search procedure; CMOS integrated circuits; Service oriented architecture; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on

Conference_Location

Seoul

ISSN

1548-3746

Print_ISBN

978-1-61284-856-3

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2011.6026465

Filename

6026465