Exploring energy-efficient DRAM array organizations

DRAM is widely used as main-memory storage in contemporary computer systems. As VLSI process technology advances, more transistors can be integrated in a single die leading to higher storage capacity and communication throughput per DRAM chip. New DRAM standards are created in order to keep up with these trends, and many factors such as performance, energy efficiency, reliability, and fabrication/testing cost are considered when a new DRAM architecture is designed. However, there are few studies on DRAM array organizations that consider both performance and energy efficiency of entire computer systems using the organizations. In this paper, we explore the design space of contemporary DRAM array organizations by varying the number of pages that can be concurrently accessed and the size of the pages. We compare various mainmemory DRAM array organizations using multithreaded and multiprogrammed workloads on a chip-multiprocessor system with die-stacked DRAM memory in search of energy-efficient array configurations.