DocumentCode
3406220
Title
Efficient estimation of dynamic power consumption under a real delay model
Author
Tsui, C.-Y. ; Pedram, M. ; Despain, A.M.
Author_Institution
Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
fYear
1993
fDate
7-11 Nov. 1993
Firstpage
224
Lastpage
228
Abstract
In CMOS circuits, glitches account for a sizeable part of the total power consumption. In this paper, we present a fast and memory efficient power estimation technique for CMOS circuits which estimates the power consumed due to the glitches. Our technique is based on the notion of tagged transition waveforms. In particular, we approximate the correlation between transition waveforms for two signal lines by the correlation between the steady state values of these lines. We obtain an order of magnitude speed up over an exact method with an average error of only 1%.
Keywords
CMOS logic circuits; CMOS circuits; average error; dynamic power consumption estimation; glitches account; real delay model; signal lines; tagged transition waveforms; transition waveforms; CMOS integrated circuits; CMOS technology; Circuit simulation; Delay estimation; Energy consumption; High performance computing; Portable computers; Power system modeling; Semiconductor device modeling; Steady-state;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1993. ICCAD-93. Digest of Technical Papers., 1993 IEEE/ACM International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-4490-7
Type
conf
DOI
10.1109/ICCAD.1993.580061
Filename
580061
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