Title :
A CT sigma-delta modulator with a hybrid loop filter and capacitive feedforward
Author :
Jhin-Fang Huang ; Yen-Jung Lin ; Kun-Chieh Huang ; Ron-Yi Liu
Author_Institution :
Dept. of Electron. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan
Abstract :
A CT (continuous-time) sigma-delta modulator (CT ΣΔM) clocked at 128 MHz with a hybrid active-passive loop filter is presented for WCDMA applications. This 5th-order loop filter architecture mainly consists of two passive integrators and three active integrators. To erase the summation amplifier used in the CIFF (chain of integrators with weighted feedforward summation) topology, the capacitive feedforward structure is employed. In addition, local feedback resistors are formed as the bridge-T network to reduce the chip area. After chip being fabricated in TSMC 0.18 μm 1.8 V CMOS technology, the overall measured results have achieved dynamic range of 62 dB over a 2 MHz signal bandwidth, SNDR of 60.26 dB, IM3 of -48 dB and power dissipation of 9 mW. Including pads, the overall chip area is 0.642 (1.07 × 0.6) mm2.
Keywords :
CMOS integrated circuits; active filters; code division multiple access; passive filters; resistors; sigma-delta modulation; 5th-order loop filter architecture; CIFF; CMOS technology; CT ΣΔM; CT sigma-delta modulator; WCDMA; active integrator; bandwidth 2 MHz; bridge-T network; capacitive feedforward structure; continuous-time sigma-delta modulator; hybrid active-passive loop filter; hybrid loop filter; local feedback resistor; passive integrator; power 9 mW; size 0.18 micron; voltage 1.8 V; weighted feedforward summation topology; CMOS integrated circuits; CMOS technology; Clocks; Noise; Solids; Switches; ΣΔM; CIFF; WCDMA; sigma-delta modulator;
Conference_Titel :
Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on
Conference_Location :
Seoul
Print_ISBN :
978-1-61284-856-3
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2011.6026516
