The practical application of retiming to the design of high-performance systems

In spite of recent advances in circuit retiming theory, especially for circuits that use level-sensitive latches, automatic retiming tools see relatively little use in practice. We suggest that the reason for the poor results reported for retiming is that it has been applied too late in the design process when there is little flexibility for performance improvement. We give an example of using retiming early in the design process to achieve better performance while at the same time simplifying the design process itself. We extend the circuit model to include clock skew, latch propagation delay, setup and hold parameters which allow retiming to generate the fastest circuit subject to a given amount of clock stew, or generate the most robust circuit with respect to skew for a given clock frequency. We illustrate these techniques using a serial-parallel multiplier circuit and show that while edge-clocked circuits require a speed margin for clock skew, level-clocked circuits can be retimed to be inherently skew-tolerant.