Investigation of delay compensation circuit techniques to reduce timing walk

Two methods are investigated to reduce the timing walk for an integrated ASIC chip to less than 1 ns without requiring an offchip delay line. In each method a delay compensation circuit is used to adjust the position of the timing marker dependent upon the size of the input signal. For signals with identical rise times a large signal will usually generate its timing pulse faster than a small signal. The first circuit is added to a monolithic constant fraction discriminator (CFD). Using one control signal based on the input signal size, an analog delay is used to delay the zero-crossing signal to the comparator for signals above a certain threshold. After analog delay compensation, the timing walk of the CFD is 660 ps or 54% of the value of the CFD without analog compensation for a signal size range of 10. The second circuit is added to a simple leading-edge discriminator. The circuit uses digital delay lines, where the length of the delay is based on the size of the input signal. The timing walk is reduced by 83%, from 4.05 ns (without digital compensation) to 700 ps (with digital compensation) for a signal size range of 8