Latchup-aware placement and parasitic-bounded routing of custom analog cells

This paper presents new results in constraint-directed placement and routing of device-level analog cells. We describe the first algorithm for latchup-aware device placement that guarantees sufficient placement of well/substrate contacts by simultaneous placement of latchup protection geometry and devices. A novel cost-to-target predictor for cost-based A/sup */ routing, and a new scheme for pruning evolving paths that violate user-supplied constrained routing of analog signals in dense placements are described. Experimental results suggest the strategy avoids the artifacts of length-for-crosstalk trade-offs seen in earlier algorithms, and allows users more fine-grain control of the routing of defense, high-performance cells. An implementation of these ideas in the tool set KA III is used to derive improved layouts from several analog cells.