Test generation for path delay faults based on learning

We present a learning-based method of generating tests to detect path delay faults in combinational circuits. The method attacks the problems related to the large numbers of faults and the large numbers of tests to detect all path delay faults directly, and in a controlled way. To achieve these goals, the method uses small versions of the circuit-under-consideration to study rules that describe the most effective test patterns, and then applies these rules to the target circuit. While learning the rules, it is possible to distinguish between rules describing critical faults and other rules, thus exploring the tradeoff between the fault coverage and the coverage of critical faults, and the number of tests. Results for several functional units are presented to demonstrate the effectiveness of the learning procedure.