A simple algorithm for fanout optimization using high-performance buffer libraries

Author

Kodandapani, K. ; Grodstein, J. ; Domic, A. ; Touati, H.

Author_Institution

Digital Equipment Corp., Hudson, MA, USA

fYear

1993

fDate

7-11 Nov. 1993

Firstpage

466

Lastpage

471

Abstract

We present an algorithm for computing minimal-area fanout networks satisfying a delay constraint. We focus on one type of fanout network structure, the fanout chain. We show that, when using libraries designed for high-speed custom CMOS chips, the fanout chain typically produces minimal-area fanout networks for a given delay constraint. We then present fast, near-optimal algorithms to compute these fanout structures.

Keywords

circuit optimisation; delay constraint; fanout chain; fanout optimization; high-performance buffer libraries; high-speed custom CMOS chips; minimal-area fanout networks; near-optimal algorithms; simple algorithm; CMOS logic circuits; CMOS technology; Circuit synthesis; Computer networks; Delay; Inverters; Logic design; Software libraries; Space technology; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1993. ICCAD-93. Digest of Technical Papers., 1993 IEEE/ACM International Conference on

Conference_Location

Santa Clara, CA, USA

Print_ISBN

0-8186-4490-7

Type

conf

DOI

10.1109/ICCAD.1993.580099

Filename

580099

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3406875