An ASIP instruction set optimization algorithm with functional module sharing constraint

This paper describes a formal method that selects the instruction set of an ASIP (application specific integrated processor) that maximizes the chip performance under the constraints of chip area and power consumption. Our contribution includes a new formalization and algorithm that considers the functional module sharing in the problem of instruction set optimization. This problem was not addressed in the previous work and considering it leads to an efficient implementation of the selected instructions. The proposed method also enables designers to predict the performance of their designs before implementing them, which is an important feature for producing a high quality design in reasonable time.