A combinational logic implementation of S-box of AES

Author

Shastry, P.V.S. ; Agnihotri, A. ; Kachhwaha, D. ; Singh, Jaskirat ; Sutaone, M.S.

Author_Institution

Dept. of Electron. & Telecommun, MKSSS´s Cummins Coll. of Eng. for Women, Pune, India

fYear

2011

fDate

7-10 Aug. 2011

Firstpage

1

Lastpage

4

Abstract

This paper presents a combinational logic based Rijndael S-box implementation for the SubByte transformation on ASIC. Combinational implementation of S-box results in low cost, small area occupancy and high throughput as compared to the typical ROM based lookup table implementation with fixed and unbreakable access time. S-box has been implemented using 0.18μm CMOS standard cell library at 1.62V and runs at clock frequency of 71.43MHz. We could achieve throughput of 571.5Mbps with core utilization of 85%, core area occupied is 39.88.4μm² using only 178 cells. Total power dissipation of the S-box implementation is 0.611mW which is quite lower than other literature available.

Keywords

application specific integrated circuits; combinational circuits; cryptography; logic design; AES; ASIC; ROM based lookup table implementation; Rijndael S-box implementation; access time; advanced encryption standard; clock frequency; combinational logic implementation; frequency 71.43 MHz; power 0.611 mW; size 0.18 mum; subByte transformation; total power dissipation; voltage 1.62 V; DVD; Encryption; Field programmable gate arrays; Three dimensional displays; US Department of Energy; AES; ASIC; Composite Field Arithmetic; S-Box;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on

Conference_Location

Seoul

ISSN

1548-3746

Print_ISBN

978-1-61284-856-3

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2011.6026559

Filename

6026559