High-speed architecture for k-dimensional LFSR in H/W implementation

Proposal for a high-speed architecture of Linear Feedback Shift Registers (LFSR), related to the hardware implementation of pseudo-random Gold-sequence, is presented here. In high-speed communication systems, a scrambling of large coded bits is difficult to compute using a conventional LFSR architecture because the requested processing time for scrambling function is very increased in proportion to length of a data stream. In this paper, we investigate the use of VLSI technology to speed up scrambling block and propose a novel LFSR architecture by generalizing an analysis of the researched architecture. The analysis of the proposed LFSR architecture demonstrates that the proposed k-dimensional LFSR architecture is k times as fast as a conventional LFSR architecture and the used processing time for scrambling is enough to implement scramble function for high-speed applications such as LTE-Advanced.