Quasi-delay-insensitive compiler: Automatic synthesis of asynchronous circuits from verilog specifications

In this paper, we present a compiler (EDA tool) that automatically synthesizes asynchronous Quasi-Delay-Insensitive (QDI) circuits from Verilog HDL specification. The proposed compiler receives Verilog HDL specification with standard coding style as input for preprocessing, and generates combinational logics and pipeline frameworks. The combinational logics can then be synthesized by commercial EDA tools, subsequently, expanded into dual-rail circuits with target library cells. Four notably interesting features in this proposed compiler are as follows. First, the resulting circuits are QDI circuits which can accommodate PVT variations. Second, the compiler accepts standard synchronous circuit specification with no special design rules to be considered. Third, this compiler adopts a data-driven pipeline, avoiding controller synthesis by configuring pipeline framework directly. Fourth, this compiler can convert single-rail to dual-rail circuits with different customized library cells. Hence, full advantage of these library cells can be taken for different requirements/applications. To demonstrate the validity and practicality of this compiler, six circuit examples based on Differential Cascode Voltage Swing Logic (DCVSL) and NULL Convention Logic (NCL) library cells are presented with simulation results. We show that our proposed compiler features better design friendliness and provides greater design flexibility.