New technique for testing of delay fault in cluster based FPGA

The recent trend of reconfigurable hardware and convergence of hardware platform in embedded system enhance application of FPGAs. Although the capability and performance of FPGA have advanced, the testing of FPGAs both online and off-line (manufacturer oriented testing) poses a major challenge. In this paper we have presented a BIST structure to test delay fault of various resources and interconnects of FPGA. The proposed scheme can be implemented for both online as well as off-line testing. We have simulated our method in Xilinx Vertex-II FPGA, using ISE tool Jbits3.0 API and XHWI (Xilinx HardWare Interface) provided by Xilinx..