Timing- and interference-free multi-layer routing tree

In this paper, we proposed the formulation of one timing-driven routing problem with consideration of interference by an efficient geometry-based approach. The objective of this work aims to simultaneously minimize the maximum length from source to target, and the potential interference nets for the multilayer routing system. Most approaches in the literatures neglected to the interference and most papers commonly improved the routing qualities by using post-processing. A space reservation technique is involved into the timing-driven router to further reduce the interference among on-chip wires and wires of boards. Second, a timing-driven partitioning which divides the entire chip into a set of sub-regions by source position is followed by the center of gravity of each sub-region to reduce the data skew. For each sub-region, the obstacle-avoiding routing algorithm is performed to connect all terminals. Experimental results show that the number of potential crosstalk nets is reduced. Moreover, the maximum length from source to target and data skew in the routing tree are improved by 35.0% and 36.3 %, respectively.