Modeling the overshooting effect of multi-input gate in nanometer technologies

Author

Li Ding ; Zhangcai Huang ; Minglu Jiang ; Kurokawa, Akira ; Inoue, Yasuyuki

Author_Institution

Grad. Sch. of Inf., Production & Syst., Waseda Univ., Kitakyushu, Japan

fYear

2011

fDate

7-10 Aug. 2011

Firstpage

1

Lastpage

4

Abstract

With the advent of nanometer age in digital circuits, the overshooting time becomes a dominating component of gate delay for CMOS logic gates. Till now, few researches have focused on the overshooting effect of multi-input gate. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32nm PTM model reflect that the proposed model is accurate within 3.6% error compared with SPICE simulation results.

Keywords

CMOS logic circuits; integrated circuit modelling; logic circuits; nanoelectromechanical devices; pulse time modulation; CMOS PTM model; CMOS logic gate; SPICE simulation; digital circuit; multiinput gate delay; nanometer technology; overshooting effect; size 32 nm; CMOS integrated circuits; CMOS technology; Computational modeling; Integrated circuit modeling; Logic gates; MOS devices; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on

Conference_Location

Seoul

ISSN

1548-3746

Print_ISBN

978-1-61284-856-3

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2011.6026587

Filename

6026587