Title :
Large scale ATM switch architecture for Tbit/s systems
Author :
Moriwaki, Norihiko ; Makimoto, Akio ; Oguri, Yozo ; Wada, Mitsuhiro ; Kozaki, T.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
This paper discusses a large-scale ATM switch architecture toward a T(tera) bit/s system. A single-stage 40-Gbit/s ATM switch was developed using a parallel processing architecture incorporating current 0.35 μm-CMOS device technology and conventional printed circuit boards (300mm×300mm approx.). This architecture is applicable to a 160-Gbit/s switch using the latest 0.25 μm-CMOS device technology. Moreover, a scalable solution for different smaller capacity switches using the same switch elements is introduced. This paper also introduces an innovative method for switch capacity extension. By employing the multipath parallel distribution approach at the cell level with cell sequence integrity guaranteed, this method enables an existing switch to be efficiently expanded
Keywords :
CMOS digital integrated circuits; asynchronous transfer mode; electronic switching systems; large scale integration; parallel architectures; printed circuits; 0.25 micron; 0.35 micron; 160 Gbit/s; 40 Gbit/s; CMOS device technology; Tbit/s systems; cell level; cell sequence integrity; large scale ATM switch architecture; multipath parallel distribution; parallel processing architecture; printed circuit boards; scalable solution; single-stage ATM switch; switch capacity extension; switch elements; Asynchronous transfer mode; CMOS technology; Hardware; Large-scale systems; Optical buffering; Optical switches; Read-write memory; Switching circuits; Telecommunication switching; Throughput;
Conference_Titel :
Global Telecommunications Conference, 1998. GLOBECOM 1998. The Bridge to Global Integration. IEEE
Conference_Location :
Sydney,NSW
Print_ISBN :
0-7803-4984-9
DOI :
10.1109/GLOCOM.1998.775751
