DocumentCode :
3407819
Title :
Exploiting temporal-jitter to counteract DPA attacks in variable-latency pipelines
Author :
Kuan Jen Lin ; Chih Ping Weng
Author_Institution :
Dept. of Electr. Eng., Fu Jen Catholic Univ., Taipei, Taiwan
fYear :
2011
fDate :
7-10 Aug. 2011
Firstpage :
1
Lastpage :
4
Abstract :
Cryptographic systems are vulnerable to Differential Power Analysis (DPA) attacks. Making the time instant of executing certain operation unpredictable is an efficient way to counteract DPA attacks. The variation of the execution time instant is called temporal jitter. In principle, the more the temporal jitter appears, the less probability the attack succeeds. In this paper, we propose specific pipeline structures which have variable latency and variable number of cascaded registers inserted in between two adjacent functional blocks. Temporal-jitter can be exploited to counteract DPA attacks in such pipelines. We will analyze their effectiveness to resist attacks. The proposed approaches can be realized in both ASIC and FPGA implementations because their structures can be easily and quickly changed without using reconfiguration facility. To show the applicability, the AES encryption algorithm was implemented and the function was successfully verified.
Keywords :
application specific integrated circuits; cryptography; field programmable gate arrays; pipeline processing; AES encryption algorithm; ASIC; DPA attacks; FPGA; cryptographic systems; differential power analysis attacks; reconfiguration facility; temporal jitter; variable latency pipelines; Cryptography;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on
Conference_Location :
Seoul
ISSN :
1548-3746
Print_ISBN :
978-1-61284-856-3
Electronic_ISBN :
1548-3746
Type :
conf
DOI :
10.1109/MWSCAS.2011.6026597
Filename :
6026597
Link To Document :
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